uRTEDemo_03_Nucleo-F446RE_SystemStates_10_Model

Core

Arm® Cortex®-M4

Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

Diagrams

Relationships

Safety

Required
The highest SIL derived from SafetyRequirements and Technical Functions.
SIL derived
-
This attribute allows to overwrite the derived SIL level. The result is the SIL effective attribute.
SIL manual
derived
The reason why the derived SIL is ignored and an explicit SIL is set.
reason
The SIL required for this implementation unit is defined by the derived SIL but can be overwritten by "SIL manual".
SIL required
-
Achieved
The achieved SIL for this implementation unit. Has to be provided by the user.
SIL achieved
QM
A justification why a certain SIL was achieved.
justification

Properties

Base
The name of this object. Certain classes of objects require this field to be unique. Please consider that this field might be used in code and thus must not contain special characters.
Name
Arm® Cortex®-M4
The type of this object within the uRTE model
Type
Core
A descriptive text for this object. Please consider that this field might be used in code and thus must not contain special characters.
Description

Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 180 MHz, MPU, 225 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions

A user defined ID which can be freely chosen. Please consider that this field might be used in code and thus must not contain special characters.
User-ID
Core_4
Each object within the uRTE model has a unique ID, this is the ID for this object
UID
_mta1cOTHEeyrV5NXTwe27Q
Core specific configuration
The ID of the core
ID
0
Ports

Software Layer

ActivationEngine

This core executes the central activation engine.

Tasks (3)

Tasks using this Core or one of its sub-components.

Task Core SIL Priority Software States Signals Init Hardware OutputSections Own TimeBase Stack

Task responsible for reading the button state

Arm® Cortex®-M4 SIL_1 6 - false .rtos.task.Button

Task responsible to let the LED blink

Arm® Cortex®-M4 SIL_1 4 - false .rtos.task.LED

Task responsible for sending out UART protocolls

Arm® Cortex®-M4 SIL_1 5 - false .rtos.task.UART